PIC18F44J50-I/ML【PDF 15/32 页】IC PIC MCU FLASH 16K 2V 44-QFN

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Sheet目录3861

11页 12页 13页 14页 [15页]16页 17页 18页 19页

PIC18F2XJXX/4XJXX FAMILY

DS39687E-page 22

2009 Microchip Technology Inc.

DSWTPS<3:0>

CONFIG3L

Deep Sleep Watchdog Timer Postscale Select bits

The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms.

1111 = 1:2,147,483,648 (25.7 days)

1110 = 1:536,870,912 (6.4 days)

1101 = 1:134,217,728 (38.5 hours)

1100 = 1:33,554,432 (9.6 hours)

1011 = 1:8,388,608 (2.4 hours)

1010 = 1:2,097,152 (36 minutes)

1001 = 1:524,288 (9 minutes)

1000 = 1:131,072 (135 seconds)

0111 = 1:32,768 (34 seconds)

0110 = 1:8,192 (8.5 seconds)

0101 = 1:2,048 (2.1 seconds)

0100 = 1:512 (528 ms)

0011 = 1:128 (132 ms)

0010 = 1:32 (33 ms)

0001 = 1:8 (8.3 ms)

0000 = 1:2 (2.1 ms)

DSWDTEN

CONFIG3L

Deep Sleep Watchdog Timer Enable bit

1 = DSWDT enabled

0 = DSWDT disabled

DSBOREN

CONFIG3L

Deep Sleep BOR Enable bit

1 = BOR enabled in Deep Sleep

0 = BOR disabled in Deep Sleep (does not affect operation in non Deep Sleep modes)

RTCOSC

CONFIG3L

RTCC Reference Clock Select bit

1 = RTCC uses T1OSC/T1CKI as reference clock

0 = RTCC uses INTRC as reference clock

DSWDTOSC

CONFIG3L

DSWDT Reference Clock Select bit

1 = DSWDT uses INTRC as reference clock

0 = DSWDT uses T1OSC/T1CKI as reference clock

MSSPMSK(1,2)

CONFIG3H

MSSP 7-Bit Address Masking Mode Enable bit

1 = 7-Bit Address Masking mode enable

0 = 5-Bit Address Masking mode enable

IOL1WAY

CONFIG3H

IOLOCK Bit One-Way Set Enable bit

1 = The IOLOCK bit (PPSCON<0>) can be set once, provided the unlock sequence has

been completed. Once set, the Peripheral Pin Select registers cannot be written to a

second time.

0 = The IOLOCK bit (PPSCON<0>) can be set and cleared as needed, provided the

unlock sequence has been completed

WPCFG(4)

CONFIG4L

Write/Erase Protect Configuration Words Page bit (valid when WPDIS = 0)

1 = Configuration Words page is not erase/write-protected unless WPEND and

WPFP<5:0> settings include the Configuration Words page

0 = Configuration Words page is erase/write-protected, regardless of WPEND and

WPFP<5:0> settings

WPEND

CONFIG4L

Write/Erase Protect Region Select bit (valid when WPDIS = 0)

1 = Flash pages, WPFP<5:0> to Configuration Words page, are write/erase-protected

0 = Flash pages, 0 to WPFP<5:0> are write/erase-protected

TABLE 5-5:

PIC18F46J11 AND PIC18F46J50 FAMILY DEVICES: BIT DESCRIPTIONS (CONTINUED)

Bit Name

Configuration

Words

Description

Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.

2: The Configuration bits are reset to ‘1’ only on VDD Reset; it is reloaded with the programmed value at any device Reset.

3: These bits are not implemented in PIC18F46J11 family devices.

4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code

protection, perform an ICSP Bulk Erase operation.

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